# The PhD-thesis switched-capacitor simulator

## Scope and source

This report reconstructs the model-generation and sizing workflow from Julia Delos Ayllón's thesis, *Towards miniaturized LED drivers: a model-centric design framework for switched-capacitor converters* (2016), using the publisher PDF as the primary source ([thesis PDF](https://pure.tue.nl/ws/files/100089602/20180620_DelosAyllon.pdf)). The PDF was downloaded and converted with `/usr/bin/pdftotext`; page references below are the thesis's printed page numbers. Repository behavior is cross-checked against the named MATLAB files. This is a symbolic averaged/loss-model generator and design tool, not a switching-transient circuit simulator.

## Direct answer

The software turns a switched-capacitor converter (SCC) architecture—component/node incidence matrices plus a switch-to-phase activation matrix—into closed-form **quantified charge-flow analysis (QFA)** equations. It symbolically solves normalized net, pumped, redistributed, and resistive-element charge multipliers, then produces conversion ratios and slow-switching-limit (SSL), fast-switching-limit (FSL), and combined output-resistance/transresistance expressions parameterized by duty cycle `D`, switch resistances (`Ron`, collectively **Sw** here), and capacitances `C`. Those expressions are subsequently evaluated or minimized to choose capacitor allocation, switch area/resistance, frequency, and components. PLECS transient simulations and prototype measurements in the thesis are later, independent validation—not part of symbolic model generation (thesis §§3.1–3.2, pp. 42–64; §5.2, pp. 87–94; Ch. 4, pp. 67–84).

## Thesis terminology and equations

- **SCC / H-SCC:** switched-capacitor converter / hybrid switched-capacitor converter. An H-SCC can load a pulse-width-modulated (**PWM-node**) and can expose multiple outputs, unlike older two-port treatments (thesis Ch. 3 introduction, pp. 41–42).
- **Target voltage** `Vtrg` and **intrinsic conversion ratio** `mi`: `Vtrg = mi Vsrc`. Under load, the output-resistance model (**ORM**) is `Vout = mi Vsrc − Io RSCC` (eqs. 3.1–3.2, pp. 42–43).
- **Charge-flow analysis (CFA)** enforces steady-state capacitor charge balance. **QFA** extends it by using a current-sink load, retaining the output capacitor, including phase duty cycles, and separating **pumped** charge (delivered continuously to the load during a phase) from **redistributed** charge (the transient equalization after switching) (thesis §§3.1.2–3.1.4, pp. 46–51).
- For phase `j`, output charge is `qout^j = Dj qout` (eq. 3.4, p. 48); normalized net charge multipliers satisfy `a_i^j = q_i^j/qout` (eq. 3.6, p. 49). Pumped multipliers are `b_i^j = I_i^j/Iout` (eqs. 3.11–3.12, p. 50). The redistributed multiplier is `g_i^j = a_ci^j − Dj b_i^j` (eq. 3.14, p. 51).
- **SSL** loss comes from capacitor charge redistribution; **FSL** loss comes from resistive elements, principally switch `Ron` and capacitor ESR. The single-output asymptotes are
  `RSSL = (1/(2 fsw)) Σ_i Σ_j (1/Ci)(a_i^j − Dj b_i^j)^2`
  and `RFSL = Σ_i Σ_j (Ri/Dj)(ar_i^j)^2` (eqs. 3.33 and 3.39, pp. 55–56). The thesis combines them as `RSCC ≈ sqrt(RSSL^2 + RFSL^2)` (eq. 3.40, p. 56).
- For multiple outputs, the **output transresistance model (OTM)** uses matrices `A^j`, `B^j`, and `Ar^j`, one output per column and component per row (eqs. 3.59–3.61, pp. 61–62). `G^j = Ac^j − Dj B^j`; row outer products yield `ZSSL` and `ZFSL`, then each total element is approximated by `ZSCC(x,y) ≈ sqrt(ZSSL(x,y)^2 + ZFSL(x,y)^2)` (eqs. 3.62–3.67, pp. 63–64). The conversion-ratio vector is the phase-sum of the input row of `A^j` (eq. 3.68, p. 64).

## End-to-end architecture-to-symbolic-model pipeline

### 1. Represent the converter architecture

**Input.** Oriented incidence matrices encode capacitors (`Acaps`) and switches (`Asw`); `Asw_act(phase,switch)` states which switches conduct in each phase. The first incidence row is the source node. [`dickson_matrix.m`](../../dickson_matrix.m) constructs Dickson capacitor and phase-switch incidence matrices; [`dickson_arch.m`](../../dickson_arch.m) interleaves phase switches and returns the `ArchDef` structure.

**Transformation.** [`generic_switched_capacitor_class.m`](../../generic_switched_capacitor_class.m) validates common node/switch dimensions, forms each phase's active incidence graph, creates symbolic `Ron1…`, `C1…`, `Resr1…`, and—unless supplied—`D1…`; it sets the last phase duty to `1 − duty`. [`SCC_Phase.m`](../../SCC_Phase.m) stores the phase graph and its charge vectors.

**Output.** A topology-independent graph representation split into phase circuits, with symbolic physical parameters. This is the executable counterpart of the thesis's per-mode circuit representation (e.g. the two 3:1 H-Dickson modes in Fig. 3.10, p. 52).

### 2. Solve net charge multipliers `A` and conversion ratios `m`

**Input.** For each phase, the code builds a tree and fundamental cut-set matrix. A cut-set equation is KCL in charge form, `Q q = 0`.

**Transformation.** [`solve_charge_vectors.m`](../../solve_charge_vectors.m) assembles one global linear system from every phase's input/capacitor/output cut-set blocks and appends steady-state capacitor charge-balance equations across phases. It solves `ax = −Qx\Qo`, partitions the result by phase into `a^j`, and sums each phase's input row to obtain `m`.

**Output.** A symbolic net-charge matrix per phase and output, plus the conversion-ratio vector. This directly implements the thesis procedure in §3.1.5 (pp. 51–54) and the matrix notation of eq. 3.59 / conversion eq. 3.68 (pp. 61–64). For the worked 3:1 H-Dickson example, duty enters via `qout^1=Dqout`, `qout^2=(1−D)qout`, so the solved `a` and `m=(2−D)/3` are symbolic functions of `D` (eqs. 3.17–3.22 and 3.42, pp. 52–57).

### 3. Solve pumped `B`, redistributed `G`, and resistive-element `Ar`

**Input.** Each phase graph, symbolic capacitances `C`, solved `a^j`, and output excitations.

**Transformation.** The class shorts the source, builds fundamental cut-set and loop matrices, substitutes capacitor impedance relationships (`1/Ci` in the loop equations), and solves a linear system for `b^j`. Thus `B` is generally a rational symbolic function of `C`; the thesis's example gives terms such as `C1/(C1+C2+C3)` (eqs. 3.23–3.28, pp. 53–54). `SCC_Phase.ar_builder` applies cut-set KCL with conducting switches and the solved `a` to recover capacitor/switch resistive charge multipliers `ar^j`. Redistributed charge is represented in code as `r = ac − b`; because the constructor duty-scales load incidence, this corresponds to the thesis `g^j = ac^j − Dj b^j` convention, but that equivalence is implicit and deserves a regression fixture.

**Output.** Symbolic `a^j(D)`, `b^j(C,D as encoded)`, redistributed vectors, and `ar^j(D)` for every output and phase.

### 4. Generate the symbolic model `f(D, Sw, C)`

`f(D, Sw, C)` is best understood as a family of closed-form outputs, not one named thesis function:

- `m(D)`: no-load conversion ratios;
- `ZSSL(D,C,fsw)` / diagonal `RSSL`: outer products of redistributed-charge rows, weighted by `1/Ci` and `1/(2fsw)`;
- `ZFSL(D,Sw)`: outer products of `ar` rows, weighted by `Ri/Dj`, where `Ri` comprises switch `Ron` and optional capacitor `Resr`;
- `ZSCC`: elementwise root-sum-square combination of the two asymptotes;
- normalized capacitor voltages, switch blocking voltages, and switch currents.

[`generic_switched_capacitor_class.m`](../../generic_switched_capacitor_class.m) implements those reductions in `gen_k_ssl`, `gen_k_fsl`, and `gen_k`; [`dickson_hybrid_topology.m`](../../dickson_hybrid_topology.m) exports symbolic `f_ssl`, `f_fsl`, `f_esr`, conversion ratios, stress data, variable lists, and substitution/evaluation closures. **Researcher interpretation:** “Sw” is not a literal thesis symbol or a single repository variable; for port planning it should mean the ordered resistive switch-parameter vector represented in MATLAB by `Ron1…RonN` (with capacitor ESR kept separate).

### 5. Feed closed forms into sizing and optimization

The thesis derives a target `RSCC` from output power/current and target efficiency, chooses the curve elbow `RSSL=RFSL`, fixes the design duty cycle, then independently sizes capacitors from the SSL equation and switches from the FSL equation (thesis §5.2, eqs. 5.3–5.9, pp. 87–89). Under total-resource constraints, minimization gives relative capacitor allocation and relative switch area; the reduced forms are `RSSL=(1/(2fsw CT)) fSSL(x)` and `RFSL=(R*/AT) fFSL(x)` (eqs. 5.10–5.11, p. 89; derivations Appendix C, pp. 127–130).

Repository roles:

- [`dickson_optimizer.m`](../../dickson_optimizer.m) and [`dickson_optimizer_ssl.m`](../../dickson_optimizer_ssl.m) substitute candidate relative capacitances into symbolic `f_ssl` and use constrained `fmincon` with positive fractions summing to one. The latter can optimize one/multiple outputs and average over duty samples.
- [`dickson_optimizer_fsl.m`](../../dickson_optimizer_fsl.m) similarly allocates normalized switch area; resistance is substituted inversely with area (`rxua./x`).
- [`implement_topology.m`](../../implement_topology.m) chooses capacitor/switch technologies satisfying voltage ratings and scales relative sizes using charge/stress metrics. This file expects an older topology schema (`ac`, `ar`, `vcb`, `vrb`) and is not directly schema-compatible with every field exported by `dickson_hybrid_topology.m`.
- [`evaluate_loss.m`](../../evaluate_loss.m) numerically evaluates SSL, FSL, ESR, bottom-plate, and switch-parasitic losses for a concrete implementation and operating point; it can solve either `Vout` or `fsw`.
- [`optimize_loss.m`](../../optimize_loss.m) numerically minimizes total evaluated loss over switching frequency and switch area.
- [`get_poles.m`](../../get_poles.m) is a later parasitic LC natural-frequency/Q estimator from concrete `C`, `L`, `Ron`, and ESR values. It is ancillary to QFA, not part of the thesis's symbolic charge-flow derivation.

A thesis example makes the handoff concrete: at `D=0.75`, SSL optimization gives relative capacitors `[0.28, 0.39, 0.23, 0.05, 0.05]` and total `CT=810 nF`; the FSL equation with identical discrete switches reduces to `RFSL=3.8 Ron` (thesis §5.2.1–5.2.2, eqs. 5.21–5.25, pp. 91–92). This is precisely why preserving symbolic expressions before numerical substitution matters.

## Symbolic generation versus numerical validation

The model generator derives algebraic asymptotes from topology, KCL/KVL, capacitor charge balance, and phase duty. It does **not** numerically integrate switching waveforms. Chapter 4 separately validates QFA against PLECS behavioral transient simulations and hardware; the thesis explicitly reports QFA predictions matching trends and compares predicted `RSCC`/transresistance with simulated and measured data (Ch. 4, especially §§4.1–4.2, pp. 67–84). Chapter 6 then validates the designed prototype; for example at `D=50%`, `fsw=2.77 MHz`, QFA predicts `RSCC=894 mΩ` versus fitted measurements of `877 mΩ` (loss fit) and `842 mΩ` (voltage fit), while predicted `K21=495 mΩ` versus measured-fit `497 mΩ` (Table 6.1, p. 99). These results validate the closed form after component values are inserted; they are not inputs to its derivation.

## Exact implications for a one-to-one MATLAB-to-C++/SymEngine port

1. **Preserve data ordering as part of the API.** Node rows, source-first branch order, capacitor columns, global switch columns, phase-local active switch order, output columns, and `symvar` substitution order all affect results. Replace implicit `symvar` ordering with explicit ordered symbol vectors while reproducing current MATLAB outputs.
2. **Port graph algebra before optimization.** Required primitives include phase contraction (`phase_conv`), tree construction, fundamental cut-set/loop matrices, source shorting, rank/echelon operations, and exact linear solves. Integer/rational incidence algebra must remain exact; premature floating point would corrupt symbolic identities.
3. **Match symbolic shapes and semantics.** `a`, `b`, `g/r`, and `ar` are matrices (component × output) per phase, not scalar coefficients. Preserve phase duties `Dj`, including the current two-phase-style final `1−D` construction, and distinguish `Ron` from `Resr`.
4. **Match formulas exactly before simplifying.** Reproduce outer-product orientation, elementwise squaring/root-sum-square, diagonal extraction, and `1/Dj` weighting. SymEngine expression trees/printing may differ from MATLAB, so tests should compare symbolic equivalence after canonical substitution and exact numeric fixtures—not strings.
5. **Separate model construction from evaluation.** The symbolic layer should return explicit `m`, `A/B/G/Ar`, `ZSSL`, `ZFSL`, `ZSCC`, stresses, and ordered parameters. Numerical substitution, constrained sizing, technology selection, loss evaluation, and transient/prototype validation should remain downstream modules.
6. **Golden tests must span the thesis chain.** At minimum use the 3:1 H-Dickson worked solution (`a`, `m=(2−D)/3`), matrix OTM dimensions/symmetry, the 5:1 design at `D=.75`, and substituted Table 6.1 values. Also test graph/sign invariance under legal tree choices.
7. **Do not equate the port with a transient simulator.** A one-to-one port reproduces QFA symbolic model generation and the repository's numerical sizing utilities. PLECS-equivalent switching simulation would be a separate product and is not implied by this code or thesis method.

## Unresolved ambiguities and risks

- **`f(D, Sw, C)` naming.** Neither the thesis nor inspected files define one object with that exact name. The supported interpretation is the bundle `m`, SSL/FSL/ESR, and combined impedance expressions. “Sw” needs a port-level definition as ordered `Ron` symbols. (Thesis §§3.1.6–3.2.6, pp. 54–64.)
- **Duty placement in `r = ac − b`.** The thesis explicitly uses `g^j=ac^j−Dj b^j` (eqs. 3.14, 3.62), while repository `get_r_vector` subtracts directly. Duty appears to be incorporated earlier through duty-scaled load incidence, but this should be proven with fixtures before translating.
- **Multiphase scope.** The generic class and solver are named multiphase, but the thesis states converters with more than two phases are outside its scope (footnote in §3.2.2, p. 61), and the class constructs the final duty as `1−obj.duty` in a way that is unambiguous only for two phases. Do not claim validated arbitrary-phase behavior.
- **Approximation scope.** `sqrt(SSL²+FSL²)` is an analytical interpolation, not an exact transient solution; the thesis notes an alternative approximation and studies error in Appendix B (eq. 3.40, p. 56; Appendix B, pp. 121–126).
- **Switching losses.** The equivalent output-resistance model excludes switching losses; the design reserves overhead, and repository `evaluate_loss` adds parasitic switching losses numerically (thesis §5.2 footnote 3, p. 88). Keep these loss categories separate.
- **Repository generations.** `implement_topology`/`evaluate_loss` consume older fields not emitted by `dickson_hybrid_topology` as inspected. A literal port must document which schema/version is authoritative rather than silently merging them.
- **Possible latent MATLAB defects.** The `half_point` branch in `dickson_hybrid_topology.m` references local matrices that are not populated after the call was replaced by `dickson_arch`; `get_poles.m` can reference `Cesr` in the three-argument path before assignment. These are port-compatibility questions, not thesis facts, and should be characterized rather than “fixed” during a one-to-one phase.

## Evidence assessment

**Direct evidence:** thesis equations, definitions, design flow, and validation tables cited above; behavior visible in the linked MATLAB sources. **Interpretation:** mapping the repository's incidence/cut-set implementation to the thesis matrix notation and treating `f(D, Sw, C)` as the exported family of symbolic functions. **Confidence:** high for QFA mathematics and the architecture-to-sizing pipeline; medium for intended behavior of under-documented/older repository branches.